25 Comments

  1. Myron Baggett
    December 7, 2018 @ 11:26 am

    After watching this I realized I failed my test. But I'm so grateful to know why I failed it. Great video!!!

    Reply

  2. MrWillis
    December 7, 2018 @ 11:26 am

    Ty

    Reply

  3. Alon Sechan
    December 7, 2018 @ 11:26 am

    Very clear and helpful.Thank you very much !

    Reply

  4. james tomlin
    December 7, 2018 @ 11:26 am

    can a invalid mode be possible if the S.R FLIP FLOP inputs are all lows and the outputs are all high? for the NOR FLIP FLOP

    Reply

  5. Иля Попов
    December 7, 2018 @ 11:26 am

    Best explanation.Clean and detailed .

    Reply

  6. fairyherb
    December 7, 2018 @ 11:26 am

    Excuse me Sir, at 27:35 , the Clock is 1, the D from High to flow, I think the Q should be follow the D. Then, the Q should be from High to Low instead of holding High. Correct me if I am wrong. Thank Sir.

    Reply

  7. Ricardo
    December 7, 2018 @ 11:26 am

    Great video Thank you.

    Reply

  8. Brian Coll
    December 7, 2018 @ 11:26 am

    Your videos are great. Thank you for taking the time to make them and help people like myself.

    Reply

  9. zain iqbal
    December 7, 2018 @ 11:26 am

    why do we only look at the highs in the grated SR flip flop timing diagram?

    Reply

  10. Bradley Gorah
    December 7, 2018 @ 11:26 am

    thanks alot

    Reply

  11. mosseh yardie
    December 7, 2018 @ 11:26 am

    this is great

    Reply

  12. Joachim Kristensen
    December 7, 2018 @ 11:26 am

    Yet again you've saved me from hours of reading! Thank you so much Sir, your lectures are amazing.

    Reply

  13. Doe normaal man
    December 7, 2018 @ 11:26 am

    first want to say i appreciate your work a lot but i am left with a question. arent the first two flipflops discussed actually latches? im talking about the sr-flipflops

    Reply

  14. Jurgens van der Spuy
    December 7, 2018 @ 11:26 am

    With the JK flip-flop, at 29:45, both are low for the first half of the clock's uptick, but the second half K goes up to reset. So do you hold or should Q go low because K goes op when the clock is still positive?

    Reply

  15. Michael Willians
    December 7, 2018 @ 11:26 am

    I'm coming for u bitch made slimy fucking bitches

    Reply

  16. Banana Banana
    December 7, 2018 @ 11:26 am

    i love you <3

    Reply

  17. skitnado25
    December 7, 2018 @ 11:26 am

    How do you build a D Flip with enable?

    Reply

  18. Nur Tem
    December 7, 2018 @ 11:26 am

    Thank you very much!

    Reply

  19. Refix King
    December 7, 2018 @ 11:26 am

    I never make comments on YouTube but I made an exception for this exceptional video. Thanks a lot. Watched it a day before my exams and I passed…had no prior info about the topic. Thanks.

    Reply

  20. Spiros Boukis
    December 7, 2018 @ 11:26 am

    Very good tutorials my friend, you are hot on passing knowledge to others. keep it up

    Reply

  21. Sean Masters
    December 7, 2018 @ 11:26 am

    Awesome Video! I haven't ever seen flip flops explained this clearly!

    Reply

  22. rajeev mulugu
    December 7, 2018 @ 11:26 am

    Can someone plz tell me what would happen​ if set and reset are 0 i asynchronous s r flip flop

    Reply

  23. VitaminFloyd
    December 7, 2018 @ 11:26 am

    Thanks! Excellent review!

    Reply

  24. Mohammed Al-Bashiri
    December 7, 2018 @ 11:26 am

    thank you very very very much for the amazing video and the amazing explanation.

    Reply

  25. M Tek
    December 7, 2018 @ 11:26 am

    Thanks Kevin Costner :p

    Reply

Leave a Reply

Your email address will not be published. Required fields are marked *